With AI as the engine, this EDA tool enables chip designers to solve the problem of “food and clothing” and move towards a “well-off”
Today the semiconductor industry is experiencing a renaissance. 5G, autonomous driving, ultra-large-scale computing, and the industrial Internet of Things are growing strongly. Behind these trends are the applications of AI and ML. The interdependence between new applications and technologies is creating demands for stronger computing, more functions, and faster data transmission speeds. So there is a new challenge for chip workers, that is, the development of next-generation chips must be faster and smarter.
To develop chips, the support of EDA tools is inevitable. EDA has developed with chips in recent decades. When the chip first appeared in the 1960s, the chip design required a completely custom layout, which was all painted by hand. With the continuous expansion of chip scale, some processes have begun to be made into standard units, which are automatically realized through schematic netlists. Later, the performance and functional requirements of the chip continued to increase, and the RTL integrated language appeared. Then there is the current automated layout and wiring. So what is the next step for EDA? Cadence’s answer is: The next step of EDA is to enter the age of machine learning.
After three years of sharpening a sword, EDA is equipped with an AI engine
Three years ago, Cadence began to explore moving EDA tools to artificial intelligence. Today, three years later, Cadence handed in a satisfactory answer. They developed a new tool-Cerebrus. According to Mr. Liu Miao, Senior Group Director of Product Engineering of Cadence Digital and Sign-off Division, the word Cerebrus comes from Latin and means brain. As the name suggests, it will combine some AI knowledge to do behaviors similar to the human brain.
Cerebrus is the industry’s first EDA tool based entirely on a machine learning artificial intelligence engine, which can expand and automate the digital chip design process. It has three key improvements: First, it is a revolution in productivity and power consumption, performance and size (PPA), that is, a revolution in chip performance. Based on unique enhanced machine learning, it can bring about 10 times Increased productivity, as well as a 20% improvement in PPA results. Second, it will bring a new RTL-to-GDS full-process automatic optimization and improve the efficiency of the design team. Third, its large-scale distributed computing provides scalable local or cloud-based design exploration to achieve faster process optimization.
The launch of Cerebrus marks the EDA industry ushered in a disruptive innovation, it represents the next leap in PPA and productivity, and also heralds the beginning of EDA tools into the ML era. Cerebrus has gone beyond ordinary EDA tools. It uses a new automatic learning method to surpass other EDA tools. The digital chip design tool centered on machine learning will give engineering teams more opportunities to play a bigger role in the project. Influence because they can say goodbye to repetitive manual processes.
On the issue of how to optimize the AI algorithm, according to Mr. Liu Miao’s explanation, Cadence’s strategy is to cooperate with industries, such as TSMC, to optimize the model through the adjustment of the process line. In addition, Cadence has a lot of data for Cerebrus to perform enhanced self-learning and find an optimal solution through probability theory.
Cerebrus is a part of the wider Cadence digital full process, which can be combined with Genus? Synthesis Solution, Innovus? Implementation System design and implementation system, Tempus? Timing Signoff Solution timing signoff solution, Joules? RTL Power Solution, Voltus? IC The Power Integrity SolutionIC power integrity solution and Pegasus? Verification System tool platforms seamlessly integrate and cooperate to provide customers with rapid design closure and better predictability. This new tool and wider design process support Cadence’s Intelligent System Design (Intelligent System Design?) strategy, which aims to drive pervasive intelligence and achieve superior design.
Cerebrus makes chip design move towards “common prosperity”
Just like the trilogy of human development, we must first solve the problem of food and clothing, and then solve the problem of well-off, and finally we can move towards common prosperity. With the aid of chip design, Cerebrus also has such a deep meaning.
Mr. Liu Miao explained that the current shortage of semiconductor talents is an urgent matter, and it is normal for companies to lack and grab people. The emergence of Cerebrus solves the most basic problem. The automatic optimization of the whole process provides guidance for many fresh graduates or students with less experience. They can use Cerebrus to quickly solve the problem of chip design and implementation. This solves the “food and clothing” problem in chip design. Of course, this is particularly in line with China’s current needs. There are so many start-ups in China that cannot find people, but they must be done. EDA tools are used to liberate people and let people do more meaningful things.
The chip must not only be designed, but the chip must be made better. This is to solve the well-off problem. Cerebrus can help engineers do various explorations. Through exploration, the optimal solution can be obtained. Not only can the chip be realized, but also Your chip performance is better than others. As in the example below, the customer expects to achieve a rate of 2GHz in the latest CPU. Cerebrus’s automatic layout planning can optimize layout planning and implementation processes at the same time, and it can be automatically adjusted in any direction, and after the adjustment is completed, you can call Innovus to find The best location gets good results. In the end, the total failure improvement was as high as 83%, and the leakage power consumption was reduced by 17%. With this, Cerebrus reached the stage of “well-off”.
A similar case is the cooperation with Renesas. With its innovative ML capabilities, Cerebrus is equipped with Cadence’s RTL-to-signoff tool process, which brings automatic process optimization and layout planning optimization, and improves design performance by more than 10%. Samsung foundries have also adopted Cerebrus and Cadence’s digital design implementation processes in multiple applications. This is because Samsung has observed that Cerebrus reduces power consumption by more than 8% on some of the most critical modules in just a few days, which in the past took months to achieve through manual operation. In addition, Samsung is using Cerebrus for automatic layout planning and power distribution network selection, which increases the final design timing by more than 50%. As Cerebrus and the digital implementation process provide better PPA results and significant productivity improvements, this solution has become a valuable addition to Samsung’s DTCO program.
Mr. Liu Miao stated objectively that Cerebrus may be able to solve 80% of the problems, but the remaining 20% of the work still needs to be done by humans. Common prosperity is beyond reach and requires the joint efforts of all mankind. Cerebrus’s meaning is to liberate humans from tedious work, to think about the 20% more valuable work, such as chip stacking, chip architecture and other more difficult tasks.
Regarding the development of Cerebrus in the future, Mr. Liu Miao also revealed: “To make the existing models more accurate, the accuracy of probability theory is also the direction we have been working hard. Then we will build our own models based on different chips and processes. Libraries, these models are not strongly related to customers.”
Concluding remarks
Looking back at the development history of Cadence for more than 30 years, from the initial pursuit of chip design excellence, to system-level innovation after 2000, to the emergence of Cerberus with AI as the engine now, Cadence has been advancing with the times and catering to The customer’s development direction.