# Application Design of Radar Signal Processing System Based on TS101S Chip

“Digital signal processing is to use some mathematical algorithms to analyze, transform, synthesize, evaluate and identify digital signals. The digital signal processor (DSP) chip, which is the core and symbol of digital signal processing, has developed rapidly since its inception, and is widely used in real-time signal processing fields such as communication systems, graphics/image processing, radar sonar, and medical signal processing. With the continuous improvement of people’s requirements for real-time signal processing and the rapid development of large-scale integrated circuit technology, digital signal processors are also undergoing rapid changes.

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Author: Zhang Xiongfei

Digital signal processing is to use some mathematical algorithms to analyze, transform, synthesize, evaluate and identify digital signals. The digital signal processor (DSP) chip, which is the core and symbol of digital signal processing, has developed rapidly since its inception, and is widely used in real-time signal processing fields such as communication systems, graphics/image processing, radar sonar, and medical signal processing. With the continuous improvement of people’s requirements for real-time signal processing and the rapid development of large-scale integrated circuit technology, digital signal processors are also undergoing rapid changes. The ADSP Tiger SHARC series processors launched by AD Company in the United States following the 16 b fixed-point ADSP21xx and 32 b floating point ADSP21xxx series are the next-generation high-performance chips based on AD2106x. This paper focuses on the performance and structural characteristics of the TS101S chip in the Tiger SHARC series, and applies it in the design of radar signal processing systems.

**1 Tiger SHARC DSP**

The key features of Tiger SHARC DSP devices are as follows:

(1) The maximum operating speed is 300 MHz, and the instruction cycle is 3.3 ns.

(2) With 6 Mb on-chip SRAM, it is divided into three 2 Mb memory blocks M0, M1 and M2, each memory block can store program, data or simultaneously store program and data.

(3) With double operation module, each operation block has 1 64 b ALU, 1 multiplier, 1 64 b shifter and 1 register group consisting of 32 registers, which can execute fixed-point and floating-point arithmetic logic and other general operations.

(4) 3 internal address/data buses, each connected to 1 of 3 internal memory blocks. The three buses are all 128 b wide, and any one bus can be used to transfer up to 4 instructions or 4 aligned data in any cycle. In this way, the TS10 1S core can access three memory blocks in parallel in any cycle, one for fetching instructions and two for accessing data.

(5) 4 link ports support point-to-point high-bandwidth data transmission, and data transmission can be performed at a rate of 250 Mb/s through a single link interface. The 4 link ports provide a good way for processor-to-processor communication with a total throughput of up to 1 Gb/s.

(6) Multi-processor characteristics, when the system composed of a single DSP chip cannot meet the processing requirements, TS101S is connected with other TS101S through external ports or link ports to form a multi-processor system. The external bus of TS101S supports parallel bus connection of up to 8 DSPs plus Host processor. When forming a multi-processor system, no matter whether the processors adopt the shared bus mode or the link port interconnection mode, no additional control is required to achieve seamless connection, and the parallel bus can be 800 Mb/s. rate for data transmission.

(7) There are DMA and SDRAM controllers, with 14 DMA channels, which provide zero-overhead data transmission without the intervention of the processor core. The address and data pins of SDRAM can be directly connected to Tiger SHARC. In addition, Tiger SHAR C provides a dedicated addressing space to support SDRAM.

The main performance indicators of TS101S are shown in Table 1.

**2 The realization of the signal processing system**

Figure 1 shows the hardware block diagram of a radar signal processing system. In order to simplify the system hardware and reduce the connection between DSP chips, the four DSPs of the system are connected in a loosely coupled link mode and share a piece of FPGA.

First, DSP1 reads the I and Q data after IF demodulation through external DMA, and DSP1 performs pulse compression (matched filtering) on the read data, and performs secondary cancellation after pulse compression to eliminate fixed clutter. The total number of distance units in the design is 2000, and 2 048 complex FFTs need to be done. When the 2 048 complex FFT is completed, it must be multiplied by the pre-stored matched filter coefficient H(k), generally 2 048 complex numbers need to be done. Multiplication, multiplication results need to do 2 048-point complex IFFT to obtain pulse compression results. It takes about 200 μs for Tiger SHARC DSP to do 2 048-point complex FFT and IFFT (operating at 250 MHz). The dual operation block and single instruction multiple data (SIMD) feature of Tiger SHARC DSP are used to perform complex multiplication of two distance units at the same time. 2 048 complex multiplications take only 25 μs. The quadratic cancellation requires 2 subtractions and 1 addition for each distance unit, and the quadratic cancellation for 2 000 distance units takes about 50 μs. It takes about 300 μs for the DSP to complete the above operation.

DSP2 and DSP3 complete the moving target detection function. When using a narrowband Doppler filter bank, in order to reduce side lobes, a sliding window weighted FFT method can be used in the system. When the number of distance units is 2 000, the processing time is about 640 μs, and two DSPs can be used for parallel processing. accomplish.

The modulo is calculated by an approximation algorithm, and each distance unit only needs to do 1 comparison and 1 addition.The constant false alarm processing first performs the average operation of the selected large unit, and then compares and judges the detected unit, thereby reducing the

false alarm rate. Accumulation is done by means of simple accumulation and averaging. The above three kinds of operations are realized by DSP4.

FPGA plays an auxiliary role in the circuit, performs data registration and distribution in the case of a large amount of data, and can also undertake the work of DS P4, and can also perform parallel/serial conversion of data if necessary.

**3 Use of Tiger SHARC DSP**

In order to ensure that Tiger SHARC DSP can work normally, the design of power-on reset signal is very important. The power-on reset waveform requirements are shown in Figure 2, but it should be noted that tSTARTLO must be greater than 1 ms after power supply is stable, tPULSE1HI must be greater than 50 system clock cycles, and less than 100 system clock cycles, and tPULSE2LO must be greater than 100 system clock cycles , After the DSP is powered on, if it needs to be reset normally, its low-level duration must be greater than 100 system clock cycles.

Tiger SHARC DSP has 3 power supplies, of which digital 3.3 V powers I/O, digital 1.2 V powers DSP core, and analog 1.2 V powers internal phase-locked loop and frequency multiplier circuit. The Tiger SHARC DSP requires that the digital 3.3 V and 1.2 V should be powered up at the same time. If strict synchronization is not possible, ensure that the core power supply 1.2 V is powered on first, and the I/O power supply is powered on after 3.3 V. In this system, a large capacitor is connected in parallel with the digital 3.3 V input, and a small capacitor is connected in parallel with the digital 1.2 V input. The purpose is to ensure that the 3.3 V charging time is greater than the 1.2 V charging time, so as to solve the problem of power supply successive problems.

The maximum current of Tiger SHARC DSP core is 1.277 A, which is the parallel operation of 4 16 b fixed-point word multiplication and addition and 2 4-word reads under the single instruction multiple data (SIMD) mode of the DSP, as well as from the external port to the internal memory. Current required for DMA operation. In fact, the size of the DSP core current is also related to the core operating frequency. Therefore, the current supplied to the DSP core can be determined according to different parallel processing tasks and core operating frequencies, and the maximum core power consumption is 1.534 W. The power consumption of the external port (for VDDIO) is mainly the power consumption of the output pin (for example, a certain bit of the data line is converted from high to low, or from low to high), and the power consumption has nothing to do with the system, generally 0.45 W . From this, it can be estimated that the power consumption of the signal processing system is about 10 W.

**4 Conclusion**

This paper introduces the application of multi-chip Tiger SHARC DSP in the radar signal processing system. The system makes full use of the high-speed computing capability and data throughput of TS101 S to perform parallel processing on different distance unit segments. In this paper, the computational complexity, time required and the number of DSPs required to complete the algorithm are analyzed, and several issues that need to be paid attention to in the process of DSP application are discussed, which has strong practicability. The system is connected to a computer bus, reserved a link port, and is designed in the mode of a signal processing general-purpose board. That is to say, when the single board resources are not enough, the signal processing capability can be doubled by increasing the number of boards. The development of a new type of radar has played a multiplier role, greatly shortened the research and development cycle, and has a wide range of application values.

Author: Zhang Xiongfei

Digital signal processing is to use some mathematical algorithms to analyze, transform, synthesize, evaluate and identify digital signals. The digital signal processor (DSP) chip, which is the core and symbol of digital signal processing, has developed rapidly since its inception, and is widely used in real-time signal processing fields such as communication systems, graphics/image processing, radar sonar, and medical signal processing. With the continuous improvement of people’s requirements for real-time signal processing and the rapid development of large-scale integrated circuit technology, digital signal processors are also undergoing rapid changes. The ADSP Tiger SHARC series processors launched by AD Company in the United States following the 16 b fixed-point ADSP21xx and 32 b floating point ADSP21xxx series are the next-generation high-performance chips based on AD2106x. This paper focuses on the performance and structural characteristics of the TS101S chip in the Tiger SHARC series, and applies it in the design of radar signal processing systems.

**1 Tiger SHARC DSP**

The key features of Tiger SHARC DSP devices are as follows:

(1) The maximum operating speed is 300 MHz, and the instruction cycle is 3.3 ns.

(2) With 6 Mb on-chip SRAM, it is divided into three 2 Mb memory blocks M0, M1 and M2, each memory block can store program, data or simultaneously store program and data.

(3) With double operation module, each operation block has 1 64 b ALU, 1 multiplier, 1 64 b shifter and 1 register group consisting of 32 registers, which can execute fixed-point and floating-point arithmetic logic and other general operations.

(4) 3 internal address/data buses, each connected to 1 of 3 internal memory blocks. The three buses are all 128 b wide, and any one bus can be used to transfer up to 4 instructions or 4 aligned data in any cycle. In this way, the TS10 1S core can access three memory blocks in parallel in any cycle, one for fetching instructions and two for accessing data.

(5) 4 link ports support point-to-point high-bandwidth data transmission, and data transmission can be performed at a rate of 250 Mb/s through a single link interface. The 4 link ports provide a good way for processor-to-processor communication with a total throughput of up to 1 Gb/s.

(6) Multi-processor characteristics, when the system composed of a single DSP chip cannot meet the processing requirements, TS101S is connected with other TS101S through external ports or link ports to form a multi-processor system. The external bus of TS101S supports parallel bus connection of up to 8 DSPs plus Host processor. When forming a multi-processor system, no matter whether the processors adopt the shared bus mode or the link port interconnection mode, no additional control is required to achieve seamless connection, and the parallel bus can be 800 Mb/s. rate for data transmission.

(7) There are DMA and SDRAM controllers, with 14 DMA channels, which provide zero-overhead data transmission without the intervention of the processor core. The address and data pins of SDRAM can be directly connected to Tiger SHARC. In addition, Tiger SHAR C provides a dedicated addressing space to support SDRAM.

The main performance indicators of TS101S are shown in Table 1.

**2 The realization of the signal processing system**

Figure 1 shows the hardware block diagram of a radar signal processing system. In order to simplify the system hardware and reduce the connection between DSP chips, the four DSPs of the system are connected in a loosely coupled link mode and share a piece of FPGA.

First, DSP1 reads the I and Q data after IF demodulation through external DMA, and DSP1 performs pulse compression (matched filtering) on the read data, and performs secondary cancellation after pulse compression to eliminate fixed clutter. The total number of distance units in the design is 2000, and 2 048 complex FFTs need to be done. When the 2 048 complex FFT is completed, it must be multiplied by the pre-stored matched filter coefficient H(k), generally 2 048 complex numbers need to be done. Multiplication, multiplication results need to do 2 048-point complex IFFT to obtain pulse compression results. It takes about 200 μs for Tiger SHARC DSP to do 2 048-point complex FFT and IFFT (operating at 250 MHz). The dual operation block and single instruction multiple data (SIMD) feature of Tiger SHARC DSP are used to perform complex multiplication of two distance units at the same time. 2 048 complex multiplications take only 25 μs. The quadratic cancellation requires 2 subtractions and 1 addition for each distance unit, and the quadratic cancellation for 2 000 distance units takes about 50 μs. It takes about 300 μs for the DSP to complete the above operation.

DSP2 and DSP3 complete the moving target detection function. When using a narrowband Doppler filter bank, in order to reduce side lobes, a sliding window weighted FFT method can be used in the system. When the number of distance units is 2 000, the processing time is about 640 μs, and two DSPs can be used for parallel processing. accomplish.

The modulo is calculated by an approximation algorithm, and each distance unit only needs to do 1 comparison and 1 addition.The constant false alarm processing first performs the average operation of the selected large unit, and then compares and judges the detected unit, thereby reducing the

false alarm rate. Accumulation is done by means of simple accumulation and averaging. The above three kinds of operations are realized by DSP4.

FPGA plays an auxiliary role in the circuit, performs data registration and distribution in the case of a large amount of data, and can also undertake the work of DS P4, and can also perform parallel/serial conversion of data if necessary.

**3 Use of Tiger SHARC DSP**

In order to ensure that Tiger SHARC DSP can work normally, the design of power-on reset signal is very important. The power-on reset waveform requirements are shown in Figure 2, but it should be noted that tSTARTLO must be greater than 1 ms after power supply is stable, tPULSE1HI must be greater than 50 system clock cycles, and less than 100 system clock cycles, and tPULSE2LO must be greater than 100 system clock cycles , After the DSP is powered on, if it needs to be reset normally, its low-level duration must be greater than 100 system clock cycles.

Tiger SHARC DSP has 3 power supplies, of which digital 3.3 V powers I/O, digital 1.2 V powers DSP core, and analog 1.2 V powers internal phase-locked loop and frequency multiplier circuit. The Tiger SHARC DSP requires that the digital 3.3 V and 1.2 V should be powered up at the same time. If strict synchronization is not possible, ensure that the core power supply 1.2 V is powered on first, and the I/O power supply is powered on after 3.3 V. In this system, a large capacitor is connected in parallel with the digital 3.3 V input, and a small capacitor is connected in parallel with the digital 1.2 V input. The purpose is to ensure that the 3.3 V charging time is greater than the 1.2 V charging time, so as to solve the problem of power supply successive problems.

The maximum current of Tiger SHARC DSP core is 1.277 A, which is the parallel operation of 4 16 b fixed-point word multiplication and addition and 2 4-word reads under the single instruction multiple data (SIMD) mode of the DSP, as well as from the external port to the internal memory. Current required for DMA operation. In fact, the size of the DSP core current is also related to the core operating frequency. Therefore, the current supplied to the DSP core can be determined according to different parallel processing tasks and core operating frequencies, and the maximum core power consumption is 1.534 W. The power consumption of the external port (for VDDIO) is mainly the power consumption of the output pin (for example, a certain bit of the data line is converted from high to low, or from low to high), and the power consumption has nothing to do with the system, generally 0.45 W . From this, it can be estimated that the power consumption of the signal processing system is about 10 W.

**4 Conclusion**

This paper introduces the application of multi-chip Tiger SHARC DSP in the radar signal processing system. The system makes full use of the high-speed computing capability and data throughput of TS101 S to perform parallel processing on different distance unit segments. In this paper, the computational complexity, time required and the number of DSPs required to complete the algorithm are analyzed, and several issues that need to be paid attention to in the process of DSP application are discussed, which has strong practicability. The system is connected to a computer bus, reserved a link port, and is designed in the mode of a signal processing general-purpose board. That is to say, when the single board resources are not enough, the signal processing capability can be doubled by increasing the number of boards. The development of a new type of radar has played a multiplier role, greatly shortened the research and development cycle, and has a wide range of application values.